1. Field of the Invention
This invention relates to semiconductor devices, and especially to a power device-driving device driving a power device such as an inverter.
2. Description of the Background Art
FIG. 55 is a block diagram schematically showing a configuration of a power device and a power device-driving device. FIG. 56 is a circuit diagram of a configuration of a principal part in a high-voltage-side driving section 101 shown in FIG. 55. FIG. 57 is a top view schematically showing the layout of the high-voltage-side driving section 101.
FIGS. 58 and 59 are cross-sectional views of a conventional structure of the high-voltage-side driving section 101, taken along the lines B-B and A-A in FIG. 57, respectively.
A technique for a high breakdown voltage IC including a bootstrap diode is disclosed, for instance, in Japanese Patent Application Laid-Open No. 2002-324848. A technique for a high breakdown voltage semiconductor device with improved latchup resistance is disclosed, for instance, in Japanese Patent Application Laid-Open No. 11-214530 (1999). A technique for a high breakdown voltage semiconductor device that employs RESURF structure is disclosed, for instance, in U.S. Pat. No. 4,292,642. A technique for a high breakdown voltage semiconductor device that employs divided RESURF structure is disclosed, for instance, in Japanese Patent Application Laid-Open No. 9-283716 (1997). A technique for a CMOS semiconductor device that reduces the occurrence of latchups resulting from a parasitic thyristor is disclosed, for instance, in Japanese Patent Application Laid-Open No. 5-152523 (1993).
In the power device and the power device-driving device shown in FIG. 55, a high-voltage-side floating offset voltage VS may fluctuate to a negative potential lower than a common ground COM during a regenerative period (namely, while a freewheel diode D2 is ON by back electromotive voltage from a load connected to a node N30). The negative fluctuations of the high-voltage-side floating offset voltage VS are transferred to a high-voltage-side floating supply absolute voltage VB via a capacitor C1, causing negative fluctuations in potential of the high-voltage-side floating supply absolute voltage VB as well.
The negative fluctuations of the high-voltage-side floating supply absolute voltage VB are transferred to n-type impurity regions 117 and 121, and n−-type impurity regions 110 and 143 in FIGS. 58 and 59. Consequently, with reference to FIG. 58, a parasitic diode PD1 between a p-type well (hereafter called “p-well”) 111 and the n−-type impurity region 110, a parasitic diode PD2 between a p−-type silicon substrate (hereafter called “p− substrate”) 200 and the n-type impurity region 117, and a parasitic diode PD3 between the p− substrate 200 and the n-type impurity region 121, all of which are reverse-biased under normal conditions, get turned on. In addition, with reference to FIG. 59, a parasitic diode PD4 between a p+-type isolation region (hereafter called “p+ isolation”) 144 and the n−-type impurity region 143, a parasitic diode PD5 between the p− substrate 200 and the n-type impurity region 143, and a parasitic diode PD6 between the p− substrate 200 and the n-type impurity region 121, all of which are reverse-biased under normal conditions, get turned on.
With reference to FIG. 59, the turn-on of the parasitic diodes PD4 to PD6 causes current to pass into the n-type impurity region 121. A CMOS 12 for outputting a high-voltage-side driving signal has a parasitic bipolar transistor PB (see FIG. 60) resulting from an n-p-n structure composed of the n-type impurity region 121, a p-well 131, and an n+-type source region 133, a parasitic thyristor PS1 resulting from a p-n-p-n structure composed of a p+-type source region 126, the n-type impurity region 121, the p-well 131, and the n+-type source region 133, and a parasitic thyristor PS2 resulting from a p-n-p-n structure composed of the p− substrate 200, the n-type impurity region 121, the p-well 131, and the n+-type source region 133. Accordingly, the current that passes into the n-type impurity region 121 resulting from the turn-on of the parasitic diodes PD4 to PD6 acts as a trigger current that causes the parasitic bipolar transistor PB to operate, or causes latchups in the parasitic thyristors PS1 and PS2. The operation of the parasitic bipolar transistor PB or latchups in the parasitic thyristors PS1 and PS2 causes an excessive current to pass through the CMOS 12, resulting in damage to circuits and components (hereafter called “latchup breakdown”) under certain circumstances.
FIG. 60 is a cross-sectional view of a simplified structure of the CMOS part, which was prepared to analyze the state of operations of the parasitic bipolar transistor PB and the parasitic thyristor PS2 resulting from the turn-on of the parasitic diode PD6. For convenience' sake, the positional relationship of an nMOSFET and a pMOSFET in FIG. 59 is reversed in FIG. 60. A VS electrode and an NMOS source electrode (nS) in FIG. 60 both correspond to an electrode 134 in FIG. 59, while a VB electrode, a pMOS back gate electrode (pBG), and a pMOS source electrode (pS) in FIG. 60 all correspond to an electrode 128 in FIG. 59. FIG. 61A shows a simplified FIG. 60 structure, and FIG. 61B shows an impurity concentration profile from the upper surface of an n+-type impurity region 127 toward a depth direction of the p− substrate 200, with respect to a position where the pMOS back gate electrode is formed in FIG. 61A.
FIG. 62 is a graph showing, upon application of a voltage to a bulk electrode in FIG. 60, namely upon application of a negative voltage (hereafter called “VS negative voltage”) to the VS electrode, the value of current passing through each of the bulk electrode, the pMOS source electrode, and the nMOS source electrode. It is shown that the current passing through the nMOS source electrode increases with an increase in negative application of the VS negative voltage, and becomes almost the same as the current passing through the pMOS source electrode when the VS negative voltage is approximately −40 V.
FIG. 63 shows current distribution when the VS negative voltage in FIG. 62 is −17 V. It is shown that current does not pass through the nMOS source electrode when the VS negative voltage is −17 V, not causing the parasitic thyristor PS2 is FIG. 60 to operate.
FIG. 64 shows current distribution when the VS negative voltage in FIG. 62 is −43 V. It is shown that current passes through the nMOS source electrode when the VS negative voltage is −43 V, causing the parasitic thyristor PS2 is FIG. 60 to operate.
FIG. 65 is a cross-sectional view of the conventional high breakdown voltage semiconductor device that employs RESURF structure (see U.S. Pat. No. 4,292,642 mentioned above), showing an extracted region where a high breakdown voltage MOS 11 is formed from the FIG. 58 structure. For convenience' sake, the positional relationship of a drain region 118 and a source region 112 in FIG. 58 is reversed in FIG. 65.
FIG. 66 is a graph showing electric fields upon application of a high voltage across a drain electrode 119 and a source electrode 114 by short-circuiting the source electrode 114 and an electrode 116aa connected to a gate electrode 116a, with respect to the FIG. 65 structure. FIG. 66 shows an electric field on the upper surface of the n−-type impurity region 110 (Si surface), and an electric field at the interface between the n−-type impurity region 110 and the p− substrate 200 (n−/p− substrate-junction depth).
It is shown in FIGS. 65 and 66 that electric field peaks on the Si surface are a peak P1 located in a position that corresponds to the right edge lower part of the drain electrode 119, a peak P2 located in a position that corresponds to the left edge lower part of the electrode 116aa, and a peak P3 located in a position that corresponds to the left edge lower part of the gate electrode 116a. Thus, a plurality of electric field peaks appear on the Si surface when RESURF structure is employed.
It is also shown in FIGS. 65 and 66 that an electric field peak in the n−/p− substrate-junction depth is a peak P4 located in the right lower edge part of the n-type impurity region 117. Since the electric field value at the peak P4 is higher than the respective electric field values at the peaks P1 to P3, a position that corresponds to the peak P4 reaches most quickly a breakdown critical electric field upon application of a voltage across the drain electrode 119 and the source electrode 114. Accordingly, the breakdown voltage of semiconductor device is determined by the peak P4 in the n−/p− substrate-junction depth when RESURF structure is employed.
FIG. 67 is a cross-sectional view showing an extracted region where a high breakdown voltage diode 14 is formed from the FIG. 59 structure. For convenience' sake, the positional relationship of an anode and a cathode in FIG. 59 is reversed in FIG. 67.
FIG. 68 is a graph showing electric fields upon application of a high voltage across an anode electrode 145 and a cathode electrode 142 with respect to the FIG. 67 structure. FIG. 68 shows an electric field on the upper surface of the n−-type impurity region 143 (Si surface), and an electric field at the interface between the n-type impurity region 121 and the p− substrate 200 (n/p− substrate-junction depth). It is shown in FIGS. 67 and 68 that an electric field peak is a peak E0 located in the right lower edge part of the n-type impurity region 121.
FIG. 69 shows potential distribution (equipotential lines) and current distribution upon application of a high voltage across the anode electrode 145 and the cathode electrode 142 with respect to the FIG. 67 structure. It is shown that the curvature of equipotential lines is great and the space between adjacent equipotential lines is narrow at a position that corresponds to the peak E0.
FIG. 70 is a cross-sectional view of the conventional high breakdown voltage semiconductor device that employs divided RESURF structure (see Japanese Patent Application Laid-Open No. 9-283716 (1997) mentioned above), showing an extracted region where the high breakdown voltage MOS 11 is formed from the FIG. 58 structure. For convenience' sake, the positional relationship of the drain region 118 and the source region 112 in FIG. 58 is reversed in FIG. 70. Divided RESURF structure is sometimes employed due to the easy fabrication thereof for a high breakdown voltage MOS of which a breakdown voltage of 600 V or higher is required.
FIG. 71 is a graph showing electric fields upon application of a high voltage across the VB electrode (which corresponds to the electrode 128 in FIG. 58) connected to the n+-type impurity region 127 and the source electrode 114 by short-circuiting the source electrode 114 and the electrode 116aa through the application of a voltage of approximately 15 V across the VB electrode and the drain electrode 119, with respect to the FIG. 70 structure. FIG. 71 shows an electric field on the upper surface of the p−substrate 200 (Si surface), and an electric field at the interface between each bottom surface of the n-type impurity regions 121 and 117, and the p substrate 200 (n/p31 substrate-junction depth).
It is shown in FIGS. 70 and 71 that an electric field peak on the Si surface is a peak E2 almost at the center of the p− substrate 200 in a divided RESURF portion, and electric field peaks in the n/p− substrate-junction depth are a peak E1 located in the right lower edge part of the n-type impurity region 121, and a peak E3 located in the right lower edge part of the n-type impurity region 117.
FIG. 72 shows potential distribution (equipotential lines) and current distribution upon application of a high voltage across the VB electrode and the source electrode 114 by short-circuiting the source electrode 114 and the electrode 116aa through the application of a voltage of approximately 15 V across the VB electrode and the drain electrode 119, with respect to the FIG. 70 structure. It is shown that the curvature of equipotential lines is great and the space between adjacent equipotential lines is narrow at positions that correspond to the peaks E1 to E3.